TITLE:

DISSERTATION PROPOSAL PRESENTATION – CONFIGURABLE SYSTEM-ON-A-CHIP IMPLEMENTATIONS FOR DECODING OF LOW-DENSITY PARITY CHECK CODES (No. 79)

DATE:

Friday, September 9th, 2005

TIME:

3:30 PM

LOCATION:

GMCS 214

SPEAKER:

Raymond Moberly, CSRC, San Diego State University

ABSTRACT:

This presentation is a proposal for doctoral research that brings together Low Density Parity Check (LDPC) codes, a leading area of Information Theory reseach, and modern Configurable System-on-a-Chip (CSOC) technology. LDPC codes are used for error correction in data communication and data storage applications. Their error correction performance, when decoded with an iterative soft-decision algorithm, is far better than previous methods of coding. The term System-on-a-Chip (SOC), describes a class of 21st century devices that combine various cores (including processors), programmable logic, combinatorial logic, and mixed signal circuits into a single silicon chip. An off-the-shelf variant, the CSOC, is suitable for a system implemented using a combination of software and programmable logic. The proposed research will use the Xilinx Vertex II Pro for implementing an iterative soft-decision LDPC decoder. The presentation will discuss strategies for obtaining optimum performance suitable for commercial use. The flexible and reprogrammable decoder implementation will permit testing of many codes in class of affine permutation-based LDPC codes being studied within our SDSU Communications Mathematics group.

HOST:

Michael O’Sullivan

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