Automatic Performance Optimization for Analog IC Design

April 11, 2025

TIME: 3:30 PM

LOCATION: GMCS 314

SPEAKER: Poki Chen,National Taiwan University of Science and Technology, Dept. of Electronic and Computer Engineering

ABSTRACT: The fine-tuning process of analog integrated circuit design is both time-consuming and labor-intensive. To assist analog IC designers who are new to software development and eager to enhance design efficiency, a simple auto-optimization method based on a genetic algorithm has been explored. This method incorporates prior work as the foundation of the automated optimization process and improves its performance. To demonstrate the capability of the outlined method, two circuits—an all-MOS relaxation oscillator (ROSC) and a 1GS/s 10-bit digital-to-analog converter (DAC)—are optimized. After optimization, the ROSC circuit shows improvements from a 0.9813 MHz operating frequency, a 43.8 ppm/°C temperature coefficient, and a 164.6 dB overall figure of merit, to a 7.023 MHz operating frequency, a 29.82 ppm/°C temperature coefficient, and a 182.2 dB overall figure of merit. Similarly, the DAC circuit shows improvements from an INL of -5.34 to 2.65 LSB and an overall figure of merit of 186.23 dB, to an INL of -2.23 to 1.07 LSB and an overall figure of merit of 223.07 dB. The substantial improvements observed in both circuits after applying this method demonstrate that such a simple and free approach can be highly beneficial for analog IC designers looking to incorporate automation into their workflow.

HOST: Shangping Ren

VIDEO: